CPCI-CAN/400-2

2x CAN: Layer 2, CANopen or ARINC 825, Optional PXI-Interface

Under Development - Available Q3 2011

• 2x CAN ISO 11898
• ARINC 825 protocol available
• 33/66 MHz CompactPCI interface

CPCI CAN Interface

The CPCI-CAN/400-2 is a CompactPCI board in 3U format that features two electrically isolated CAN High-Speed interfaces according to ISO 11898-2. CAN is driven by the esd Advanced CAN Core (esdACC) CAN controller implemented in the Xilinx Spartan 3e FPGA. The CPCI-CAN/400-2 provides high-resolution hardware timestamps.

PXI Interface

The CPCI-CAN-400-2 optionally features a PXI interface. The signals TRG 0-7, CLK 10 and STAR are controlled via the FPGA. The signals LBL/LBR1-12 are looped through. The PXI interface is available on request.

Software Support

CAN layer 2 (CAN-API) software drivers are available for Windows, VxWorks, QNX, RTX1 and Linux supporting up to 24 CAN nets. Drivers for other operating systems are available on request. The CANopen software package is available for Windows, VxWorks, Linux, QNX, and RTX. ARINC 825 as another higher layer protocol is available as an option for Windows, VxWorks, QNX, Linux, and RTX.

Technical Specifications:

CompactPCI interface and microprocessor:
Interface:	PCI bus according to PCI Local Bus Specification 2.2, 32 bit 33/66 MHz, 3.3 V (5 V tolerant), PCI bus master capability
Memory:	BlockRAM: 72 KB, DRAM: 64 MB
Microprocessor:	optional 32-bit mC in FPGA (MicroBlaze)
CAN:
Interface:	2x CAN high-speed interface acc. to ISO11898-2, differential, electrically isolated, bit rate up to 1 Mbit/s
CAN controller:	according to ISO 11898-1 (CAN 2.0 A/B)
General:
Ambient temp.:	standard: 0 ...+50 /C
Humidity:	max. 90%, non-condensing
Connectors:	P1, P2, 2x DSUB9 (male)
Power supply:	5 V, 3.3 V
LEDs:	CAN status, 1x module status

Order information:

Designation		order no.
CPCI-CAN/400-2	2x CAN	C.2033.02
CAN-DRV-LCD VxWorks	Object license and CD for VxWorks 5.x and 6.x	C.1101.55
ARINC825-LCD	ARINC 825 object license and VxWorks CD for VxWorks, incl. C.1101.55	C.1140.18
CAN-DRV-LCD	CAN layer 2 (CAN-API) object Windows / Linux license for Windows and Linux 1, incl. CD	C.1101.02
ARINC825-LCD Windows/Linux	ARINC825-LCD ARINC 825 object license and Windows / Linux CD for Windows and Linux, incl. C1101.02	C.1140.06
CANopen-LCD	CANopen object license for Windows and Linux 1, incl. CD	C.1101.06

CPCI-CAN/400-2

2x CAN: Layer 2, CANopen or ARINC 825, Optional PXI-Interface

Under Development - Available Q3 2011

• Optional IRIG-B, optional PXI-Interface
• 4x CAN ISO 11898
• ARINC 825 protocol available
• 33/66 MHz CompactPCI interface
• IRIG-B input (option)

Download complete Data Sheet (PDF file)

CPCI-CAN/400-2

Under Development - Available Q3 2011

Driven by esdACC (Advanced CAN Core)

Basic Product Features:

• CAN ISO 11898-1 protocol compatibility
• 11-Bit and 29-Bit CAN IDs
• Bit rates from 10kbit/s up to 1 Mbit/s supported
• Receive buffer (64 CAN messages 2)
• Complete access to CAN error counters
• Programmable error warning limit
• Error code capture register
• Error interrupt for each CAN bus error
• Arbitration lost interrupt with detailed bit position
• Single-shot transmission (no re-transmission)
• Listen only mode (no acknowledge, no active error flags)
• Automatic bit rate detection (software supported bit rate detection)
• Acceptance filter (4-byte code, 4-byte mask)
• Self-reception mode (Reception of ‘own’ messages

Superior esdACC Features:

• Operating system independently programmable via esd’s NTCAN-API
• 32-Bit register interface optimized for CAN needs
  • Easy to program
  • Transmission and reception of CAN frames with a minimum of register accesses
• RX and TX timestamping (64-Bit wide, bit accurate, resolution may vary with input clock, in any case = 62.5 ns, usually 20.833 ns)
• TX FIFO (8 CAN frames deep 2)
  • Providing the means to generate 100% busload even with non-realtime operating systems
  • Providing the means for real back-to-back transmission
• Reactive and frame accurate abortion of transmissions
  • e.g. for driver timeouts
  • ISO11898-1 conform
  • Aborted frames in FIFO not blocked by low priority TX
• Hardware timer to provide accurate software timeouts beyond operating system accuracy
• Bus mastering in RX direction takes the load off host CPU (needs bus master capable local bus to host interface)
• Optional integration w/ 32-Bit microcontroller to give further relief to host CPU
• Optional sources for timestamps (e.g. IRIG-B)
• FPGA technology allows tailoring features to customer needs, incl. optional integration w/customer FPGA content.
• Driver Availability: Windows, Linux, QNX 1, VxWorks 1, RTX 1
• Available higher-level protocols: CANopen, ARINC825, J1939

For further information on the esdACC IP Core, please contact our sales team.