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Home > Hardware > AMC >
AMC-CAN4 4 Channel AMC CAN Module
AMC-CAN4
Item #: U.1002.01
Availability: Normally Stocked
Usually ships In 2 Weeks
AMC-CAN4
4 Channel AMC CAN Module
Under Development - Available Q1 2012
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Cost
effective: 4 channels onboard
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High
performance: local data management by FPGA and bus mastering
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Wide
software support: drivers for Windows, Linux, QNX and other operating systems
AMC
CAN Interfaces
The
AMC-CAN4 features four CAN High-Speed interfaces according to ISO 11898-2. The
CAN interfaces are electrically isolated against the controller potential and
against each other. CAN status is displayed by two LEDs for each CAN channel
placed at the RJ45 connectors.
CAN
Data Management
The
four independent CAN nets according to ISO 11898-1 are driven by the esd
Advanced CAN Core (esdACC) CAN controller implemented in the Xilinx Spartan 3e
FPGA.
Controlled by the FPGA the AMC-CAN4 supports PCI bus mastering as an
initiator, meaning that it is capable of initiating write cycles to the host
CPU’s RAM independent of the CPU or the system DMA controller. This results in
a reduction of overall latency on servicing I/O transactions in particular at
higher data rates.
Software
Support
CAN
layer 2 (CAN-API) software drivers are available for Windows, RTX, VxWorks*,
QNX* and Linux* supporting up to 24 CAN nets. Drivers for other operating
systems are available on request.
The
CANopen® software package is available for Windows, VxWorks*, RTX*, QNX* and
Linux*. The J1939 software package is available for Windows, VxWorks*, QNX* and
Linux*.
Technical
Specifications:
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MicroTCATM/AMC®
standards:
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mTCA:
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PICMG®
MTCA.0 R1.0, PICMG® AMC.0 R2.0
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IPMI:
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IPMI V1.5, controller Atmel® AVR
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Updates
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PICMG® HPM.1 R1.0
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PCIe
bridge:
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PCISIG® PCIe spec. R.1.0a
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CAN
interfaces:
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CAN
controller:
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esdACC in FPGA Spartan® 3e, acc. to ISO
11898-1 (CAN 2.0 A/B)
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Physical
interface:
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4x CAN high-speed interface acc. to ISO
11898-2, electrically isolated, bit rate up to 1 Mbit/s
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CAN
connector:
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4x RJ45, pin assignment acc. to CiA DR303-1
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General
:
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Dimensions:
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mid-height,
single-width (73.5 x 180 mm) AMC
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Ambient
temp.:
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0 ...+70 /C (free convection)
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Humidity:
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max. 90 %, non-condensing
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Power
supply:
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3.3 V (I3.3VMPMAX= 70 mA), 12 V (I12VTYPICAL
= 0.4 A, I12VMAX= 0.5 A)
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Connectors:
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J1:
AMC B/B+ compatible (MicroTCATM)
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LEDs:
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blue
(hot plug), red (IPMI), green (OK), 4x yellow and 4x green (CAN status)
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Order
information:
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Designation
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Order
no.
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AMC-CAN4
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4x
CAN interface, acc to ISO11898-2
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U.1002.01
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AMC-CAN-RJ45-DSUB9
cable
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Adapter
cable RJ45 male to 9-pin DSUB male connector, length 1.5 m
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U.1002.10
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CAN-DRV-LCD
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Object
license for Windows and Linux incl. CD-ROM
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C.1101.02
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Driven
by esdACC (Advanced CAN Core)
Basic
Product Features-
CAN
ISO 11898-1 protocol compatibility
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11-Bit
and 29-Bit CAN IDs
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Bitrates
from 10kbit/s up to 1 Mbit/s supported
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Receive
buffer (64 CAN messages *)
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Complete access to CAN error counters
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Programmable
error warning limit
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Error
code capture register
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Error
interrupt for each CAN bus error
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Arbitration
lost interrupt with detailed bit position
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Single-shot
transmission (no re-transmission)
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Listen
only mode (no acknowledge, no active error flags)
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Automatic
bitrate detection (software supported bit rate detection)
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Acceptance
filter (4-byte code, 4-byte mask)
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Self
reception mode (Reception of ‘own’ messages)
Superior
esdACC Features:-
Operating
system independently programmable via esd's NTCAN-API
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32-Bit
register interface optimized for CAN needs
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Easy
to program
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Transmission
and reception of CAN frames with a minimum of register accesses
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RX
and TX timestamping (64-Bit wide, bit accurate, resolution may vary with input
TX
FIFO (8 CAN frames deep *)
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Providing
the means to generate 100% busload even with non-realtime operating systems
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Providing
the means for real back-to-back transmission
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Reactive
and frame accurate abortion of transmissions
- e.g. for driver timeouts
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ISO11898-1
conformant
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Aborted
frames in FIFO won't be blocked by low priority TX
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Hardware timer to provide accurate software timeouts beyond operating system accuracy
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Bus
mastering in RX direction takes the load off host CPU (needs bus master capable local bus to host interface)
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Optional
integration with 32-Bit microcontroller to further relieve host CPU
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Using
FPGA technology provides the option to tailor any feature to any customer's
needs, including optional integration with customer's FPGA content
*Note: Buffer sizes might vary to customer's needs.
Driver
Availability:-
Windows,
Linux, QNX, VxWorks, RTX
Available
higher level protocols:-
CANopen,
ARINC825, J1939
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For
further information on the esdACC IP Core please contact our sales team.
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